In an integrated circuit memory device such as a dynamic random access memory (DRAM), a memory cell capacitor is used to store a bit of information. As the integration densities of these memory devices increase, however, the area of each memory cell capacitor may be reduced. The memory cell capacitance, however, should be maintained or increased to provide an adequate margin with respect to soft errors generated by .alpha.-rays and noise. To maintain the desired capacitance while decreasing the size of a memory cell capacitor, methods have been adopted using a ferroelectric layer having a relatively high dielectric constant or increasing an effective area of the capacitor electrode. In particular, the effective area of a capacitor electrode can be increased using a hemispherical grained electrode.
A method for forming a hemispherically grained electrode for a capacitor will now be discussed with reference to FIGS. 1 through 4. As shown in FIG. 1, a field oxide layer 12 is formed on a semiconductor substrate thus defining active and field areas of the semiconductor substrate 10. An interlayer insulating layer 14 is formed on the substrate 10 and the field oxide layer 12, and a first photoresist pattern 16 exposes a portion of the insulating layer 14 opposite an active area of the semiconductor substrate 10. The insulating layer 14 is then etched using the first photoresist pattern 16 as an etching mask to form a contact hole 18 exposing a portion of an active area of the substrate.
The first photoresist pattern 16 is then removed, and a conductive layer 20 is formed on the insulating layer 14 filling the contact hole 18 as shown in FIG. 2. In particular, the conductive layer 20 is formed from a layer of doped silicon, and the conductive layer 20 is in electrical contact with the substrate 10. The conductivity of the conductive layer 20 is determined by the dopant concentration thereof. The dopant concentration of the conductive layer 20, however, also influences the size of the hemispherical grains of silicon which will be formed thereon. Generally, the size of hemispherical grains increases as the dopant concentration decreases. If the dopant concentration of a capacitor electrode is too low, a minimum (C.sub.min)-to-maximum (C.sub.max) ratio (C') of the capacitance of the resulting capacitor may be decreased. The resistance of the capacitor to soft errors may be reduced with a low C' value thus increasing the likelihood that stored data may be lost. Accordingly, there is a lower limit to the dopant concentration allowable for the lower electrode.
In addition, the portion of the conductive layer 20 in the contact hole 18 provides an electrical path from the capacitor electrode to the substrate. If the resistance of this conductive path is increased by lowering the dopant concentration of the conductive layer 20, however, the operational speed of the capacitor may decrease and the overall operation of the memory device may be slowed. Accordingly, the conductive layer 20 is typically doped to a concentration in the range of 10.sup.19 to 10.sup.21 atoms per cm.sup.3. A C' value of about 0.9 can be obtained for a capacitor including the electrode discussed above having a dopant concentration in the range of 10.sup.19 to 10.sup.21 atoms per cm.sup.3.
A second photoresist pattern 22 is formed on the conductive layer 20 as shown in FIG. 2. This second photoresist pattern 22 is used as a mask when patterning the conductive layer 20. In particular, the conductive layer 20 is etched using the second photoresist pattern 22 as an etching mask to form a lower electrode 20a for a capacitor as shown in FIG. 3. The second photoresist pattern 22 is then removed.
Grain seedlings are formed on the lower electrode 20a by injecting silane (SiH.sub.4) or disilane (Si.sub.2 H.sub.6) gas into a reaction chamber. The gas supply used to form the grain seedlings is then interrupted, and the lower electrode 20a with the grain seedlings is annealed at a predetermined temperature. Hemispherical silicon grains are formed centered around the grain seedlings thus forming an HSG layer 26 on the surface of the lower electrode 20a, as shown in FIG. 4. A capacitor using hemispherical grained-Si is discussed, for example, in the reference by Watanabe et al. entitled "A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) for 256 Mb DRAMS," IEDM 92-259, 1992 IEEE, pp. 10.1.1 to 10.1.4. A dielectric layer is then formed on the HSG layer 26, and a conductive layer is formed on the dielectric layer to provide the second capacitor electrode.
As discussed above, the dopant concentration of the lower electrode should be increased to 10.sup.19 to 10.sup.21 atoms per cm.sup.3 to provide a desired C' value. Because the size and reproducibility of the hemispherical silicon grains are inversely proportional to the dopant concentration of the lower electrode, the size of the hemispherical silicon grains increases as the dopant concentration decreases. Conventional capacitor electrodes fabricated to provide a predetermined C' value, however, may have sufficiently high dopant concentrations that the reproducibility and size of the hemispherical silicon grains are less than desired. The reduced reproducibility may result in a difference in electrode surface areas between capacitors so that the capacitance of different capacitors vary. Accordingly, conventional methods for forming hemispherical silicon grains may be unable to provide a desired reliability when device integration is increased.